Half adder (Using gates and behavioural code)

Let’s see how we can implement synchronous half adder using gates and also by using behavioural modelling.

Using Gates:


module half_adder_using_gates(
input clk,
input a,b,
output reg sum,carry
);

always@(posedge clk)begin
sum <= a^b;
carry <= a&b;
end

endmodule

Behavioural modelling:


module half_adder(
input clk,
input a,b,
output reg sum,carry
);

always@(posedge clk)begin
{carry,sum} = a+b;
end

endmodule